1. Field of the Invention
This invention relates in general to data bus systems, and more particularly to bi-directional data bus circuits using two-state logic.
2. Description of the Related Art
Digital electronics are circuits in which there are usually only two states possible at any point, usually referred to as a HIGH level voltage (a logic 1) or a LOW level voltage (a logic 0).
Normally, a logic circuit will not operate correctly if the outputs of two or more gates or flip-flops are directly connected to each other. For example, if one gate has a LOW and another has a HIGH, when the gate outputs are connected together the resulting output voltage may be some intermediate value that does not clearly represent either a LOW or a HIGH. In some cases, damage to the gates may result if the outputs are connected together. What is needed is a gate whose output can be "open". Use of three-state logic will permit the outputs of two or more gates or flip-flops to be connected together.
Three-state logic, also called Tri-state logic (a trademark of National Semiconductor Corporation) is a gate with a third output state: open circuit. A separate enable input determines whether the output behaves like an ordinary active two-state output or goes into the "third" (open) state, regardless of the logic levels present at the other inputs. A device with three-state output behaves exactly like ordinary active two-state logic when enabled, always driving its output either HIGH or LOW; when disabled, it effectively disconnects its output, so another logic device can drive the same line. Three-state drivers are widely used to drive computer data buses which are, for example, a single set of eight or sixteen wires accessible to several devices. Every device (memory, peripherals, etc.) that needs to put data on the shared bus ties onto it with three-state gates. The network is arranged so that at most one device has its drivers enabled at any instant, all other drivers being disabled into the open (third) state. However, there must be some external logic to make sure that three-state devices sharing the same output lines don't try to drive the lines at the same time (which produces an undesirable condition called "bus contention").
As shown in FIG. 1A, labeled prior art, three-state element 100 has two input lines 105 and 110, data input line 105, and control or enable input line 110, and one output line 115. Data input line 105 provides a data input signal to the three-state element 100 with either a logic value of 0 or 1. When the enable signal on control input line 110 is active, the logic level of the data input signal is transferred through element 100 to output line 115. When the enable signal on control input line 110 is inactive, output line 115 is at a high impedance state. Thus the output signal from the three-state element 100 can be in one of three states, logic 0, logic 1, or high impedance.
In a digital circuit, three-state elements are often used to construct three state buses such as bus 120 illustrated in FIG. 1B and labeled prior art. Three-state elements 100-1, 100-2, . . . 100-n have data input lines 105-1, 105-2, . . . 105-n, respectively, that carry corresponding data input signals. Control input lines 110-1, 110-2, . . . 110-n carry an enable signal to three-state elements 100-1, 100-2, . . . 100-n, respectively. In the digital circuit, only one data input signal is selected or enabled and appears on output line 125 as a bus output signal. There are at least two possible states of bus 120 which are undesirable. In the first state, two or more control input signals are active or enabled and as a result a contention occurs on bus 120 between the output signals from the active three-state elements. In the second state, all control input signals are inactive so that bus 120 floats at a high impedance state. Both of these states are typically unacceptable in a digital circuit.
With the development of large systems today, it is becoming increasingly important to design into logic systems efficient procedures for diagnosing faults. A design for a digital circuit is typically tested by applying a sequence of known test vectors to the design using a computer based system. A test vector typically defines all the input signals to the circuit and the expected output signals for the given input signals. The main purpose of the test vectors is to help the designer verify that the design has been correctly manufactured. However, a test pattern generator in a computer based design system does not have a means for determining whether a given test vector results in either contention or floating of a three-state bus. Typically, a computer based test generation system, and therefore the test pattern generator, support a set of primitive logic elements such as AND, OR, NAND, NOR, and NOT.
Therefore, a system is needed for use in, for example, computer system data buses, that provide the benefits and functions of three-state element data buses without the problems of bus contention and floating that occur with three-state elements and also provides a more efficient and viable circuit system for circuit scan testing of the design.